The present invention relates to wafer bonding, and in particular, the bonding of wafers together, which may be accompanied by simultaneously electrically interconnecting such wafers.
Wafer-level packaging techniques can be used in a variety of applications to simultaneously make microelectronic assemblies which include a plurality of microelectronic elements, such as semiconductor chips stacked one over another with electrical interconnections between the chips. In some cases, wafer-level packaging techniques can be used to make microelectronic assemblies which include a microelectronic element having active circuit elements, such as a semiconductor chip, mounted with dielectric or semiconductor element as a packaging layer. Such techniques typically require joining a microelectronic device wafer, i.e., one having active circuit elements, with another element, which can be another device wafer or a packaging layer (e.g., cover wafer or other wafer) having the same size and shape as the device wafer.
One of the challenges of such wafer-level processing is to achieve a sufficiently planar interface between the wafers and to make reliable electrical interconnections between contacts on respective wafers. Further improvements in this respect would be desirable.
Size is a significant consideration in any physical arrangement of chips. The demand for more compact physical arrangements of chips has become even more intense with the rapid progress of portable electronic devices. Merely by way of example, devices commonly referred to as “smart phones” integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device. Complex portable devices require packing numerous chips into a small space. Moreover, some of the chips have many input and output connections, commonly referred to as “I/O's.” These I/O's must be interconnected with the I/O's of other chips. The interconnections should be short and should have low impedance to minimize signal propagation delays. The components which form the interconnections should not greatly increase the size of the assembly. Similar needs arise in other applications as, for example, in data servers such as those used in internet search engines. For example, structures which provide numerous short, low-impedance interconnects between complex chips can increase the bandwidth of the search engine and reduce its power consumption.